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High-Voltage, Linear High-Brightness LED
Driver with Open-LED Fault Detect
ELECTRICAL CHARACTERISTICS (continued)
(V IN = 12V, V FLTS = 0V, R CS = 4.07 I , V GND = 0V, DIM = unconnected, C IN = 0.1 F F (Note 2), T J = T A = -40 N C to +125 N C, unless
otherwise noted. Typical values are at T A = +25 N C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT EVENT STATUS MEMOR Y
FLTS Activation Threshold
V INTH
V IN rising, V CS = 0V
7
7.38
7.75
V
FLTS Activation Hysteresis
20
mV
LED Open Threshold
LED Open Blanking
V CSO
T B
25
14
30
25
35
50
mV
F s
Fault Voltage
FLTS Charge Current
V FLTS
I CFLTS
V IN = 40V, V CS = 0V, C FLTS = 0.1 F F
V CS P 25mV
12
0.65
15
2.8
18
4.8
V
mA
FLTS Discharge Current
FLTS Threshold To Turn Off LED
Current Sink
V FLTH
V FLTS = 0.5V
2.25
0.95
5
1.3
7.25
1.65
F A
V
DIM LOGIC
Input High Voltage
Input Low Voltage
DIM Voltage Logic Hysteresis
V IH
V IL
V DIM_HYS
2.1
0.15
0.8
V
V
V
DIM Pullup Current
DIM Pulldown Current
V DIM = 0V
V DIM = 0.8V, V IN = 2.4V
10
0.385
30
1
60
1.5
F A
mA
DIM Pulse Width
70
F s
DIM Frequency
f DIM
10
kHz
LEAKAGE CURRENTS
SINK Leakage Current
FLTS Leakage Current
V SINK = 40V, V DIM = 0V
V FLTS = 8V, V IN = 0V
1
1
F A
F A
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Temperature rising
160
15
N C
N C
Note
Note
Note
Note
Note
2:
3:
4:
5:
6:
A 51 I resistor is connected between SINK and a 6.5V supply to reduce power dissipation during the factory test.
All devices are 100% production tested at T A = +25 N C. Limits over temperature are guaranteed by design.
Guaranteed by design and not production tested.
Internal switch resistance is measured with I SINK = 0.95 x I SINK0 (I SINK0 is I SINK at V SINK = 0.9V).
Supply turn-on delay will be measured by rising supply in 6 F s from GND to 12V, and measurement starts when V IN = 4V
(typical UVLO).
Note 7: DIM is kept high to avoid delay due to high capacitance from test setup. In applications, a 30 F A pullup current charges
parasitic capacitance at DIM with negligible delay. Ensure that unnecessary capacitance is not added at DIM during the
PCB layout.
_______________________________________________________________________________________
3
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